In conventional nonvolatile semiconductor memory devices (memory), elements have been integrated in a two-dimensional plane on a silicon substrate. The dimension of one element is decreased (the element is downsized) in order to increase the memory capacity of a memory, but the downsizing is becoming difficult these days in terms of cost and technique.
In contrast, a collectively processed three-dimensional stacked memory is proposed.
For example, JP-A 2009-146954 proposes a technology in which: memory holes are formed in a stacked body in which conductive layers functioning as control gates in a memory device and insulating layers are alternately stacked; a charge storage film is formed on an inner wall of the memory hole; and then silicon is provided in the memory hole to arrange memory cells three-dimensionally. If, in particular, the number of stacked layers in the stacked body increases in such a structure, it becomes difficult to form a contact structure for connecting the substrate and an interconnection above the stacked body.